Based upon statistical considerations involving the inherent defectiveness of the silicon crystal lattice, the defectiveness induced by foreign particles into the internal geometrical structures of the integrated circuits and the defectiveness induced by swings of the production process parameters into the internal structures of the integrated circuits, it can be argued that the production efficiency of the memory circuits is a monotonically decreasing function of the utilized silicon surface and in effect of the number of memory calls utilized on a single chip.
A close analysis of the damages materially caused, however, shows that the concerned memory devices have only a few rows or a few columns or a few tens of not operative locations. Furthermore, such defects can be detected only in very severe operation conditions, hardly simulatable without particular test equipment. Anyway, notwithstanding this "scarce" defect occurrence rate, said faulty memories cannot be employed in such applications as memory banks for traditional computers.
Taking as a base the observation that, since the memories as presently used can be considered as byte-oriented, the immediate solution to map all faulty bytes cannot be adopted, because as a matter of fact, such a step would require more information than one could subsequently store, this invention is based upon the concept of developing a memory array adapted to operate by blocks and then of retrieving memory blocks, rather than memory bytes, thereby renouncing to develop a byte-oriented memory array, fully compatible with the memory arrays conventionally utilized in present computers.
Based upon this concept, therefore, a first step aimed at making such memory devices utilizable provides for organizing them as memory banks in order to form an elementary information "word", as it occurs in conventional applications, and, thereafter, it provides for identifying all not-faulty homologous address locations: this is carried out at predetermined supply voltage and temperature conditions, as it will be illustrated, and, since the obtained results generally are not coincident, only those locations which have been positively tested are selected.
The result of this step, which is defined as "mapping", is stored in a not-volatile OTP memory associated to the memory bank.
The external user, who desires to retrieve the data stored in the various memory blocks, will have access to them by utilizing successive (logical) memory addresses and will exploit to this aim the operation of this not-volatile memory which will provide for transcoding the map stored therein into the (material) addresses associated to the memory banks. In other words, the access to the memory blocks is developed in two successive stages. In a first stage, the intelligent portion of the system, for instance a central processing unit (CPU), requests an access to a block identified by a sequential (logical) address. At this point, the system provides for associating the material address of a block of the memory array to said logical address. This association or transcoding operation is carried out by said not-volatile memory. As a matter of fact, the user receives a logical address from outside, gets access to said address of the OTP memory, retrieves the content thereof and utilizes it for a direct and immediate access to the correspondent material block of the memory array.
All above set forth steps, however, represent only a portion of the whole method, because:
it can be reasonably believed that the originally faulty memory chips can be degraded in the long run more easily than perfectly operating chips, and therefore, they can subsequently have faulty locations even if such locations may have originally proved as error-free,
troublesome variations of the number of error-free locations could be encountered, which could cause manufacturing problems, because it is necessary that each memory bank has a certain minimum number of error-free locations.
According to the rule, as it has already observed, all faulty locations should be identified, but this wold pose an excessively severe constraint.
Aiming at solving this problem and at providing a system adapted to be operative also when some defectiveness exists and also aiming at enlarging the number of locations wherein it is possible to store information, by utilizing also regions featuring a limited defectiveness, a second stage of the method according to this invention provides for applying techniques designed for error correction (ECC).
More particularly, the developed technique is based upon the theory of the cyclic polynomial codes and specially upon the REED-SOLOMON code with generator polynomial EQU g(x)=x.sup.4 +a.sup.201 .multidot.x.sup.3 +a.sup.246 .multidot.x.sup.2 +a.sup.201 .multidot.x+1
The R-S code has been adopted, among other, because it is not byte-oriented, but it is oriented on the base of a character string and it can be realized by acting upon the code parameters with desired redundancy. In the case of this invention, a redundancy of 12.5% has been adopted.
Since the block as not considered is a 512 byte block (such number has been adopted since it corresponds to that of a conventional peripheral equipment) and since some difficulties would be encountered in embodying such a function into a silicon wafer, it is proposed to divide the 512 byte string into various sub-strings and to determine the correction bytes for each sub-string.
Clearly, this approach does not utilize the R-S code in optimal manner. In fact, in a R-S type code, if a 512 byte string and 64 control bytes are considered, up to 32 bytes can be corrected, regardless of the positions they occupy in the string. On the contrary, thanks to the proposed division, according to which 32 byte sub-strings plus 4 control bytes are provided, only 2 bytes can be replaced in a 32 byte string and this can be made only in the considered string and cannot be made in other strings. The capability of the code is rather reduced, but the arrangement is found to be satisfactory, with respect to the number of the logic gates that should be implemented and to the whole necessary equipment.
Further details and advantages of this invention will be evident from the following specification by referring to the enclosed drawing wherein the preferred embodiment is shown by way of illustration and not by way of limitation.